SHF: Small: Compiler and Runtime Support for Computational Storage in HPC

About This Grant

This project addresses a critical challenge in high-performance computing (HPC): the growing inefficiency and energy demands of moving massive volumes of data between storage and compute units - a bottleneck that hampers scientific progress and national innovation. As the U.S. advances toward exascale computing and increasingly data-centric scientific discovery, the ability to analyze and process large amounts of data efficiently is paramount in nationally significant domains such as energy systems, artificial intelligence (AI), astrophysics, and precision health. This project focuses on Computational Storage Devices (CSDs), a transformative technology that embeds processing power directly into storage hardware, dramatically reducing data movement and enabling faster, more energy-efficient computation. However, programming and optimizing CSDs remains highly complex, limiting their impact. This project develops a scalable, automated software infrastructure (including compilers, runtime systems, and programming interfaces) that makes it practical to deploy and benefit from CSDs across diverse and critical HPC workloads of national importance. By unlocking the potential of near-storage computing, this project directly contributes to national priorities such as AI, energy systems, and advanced manufacturing. Additionally, the project produces open-source tools, CSD-focused benchmarks, and educational resources, contributing to the U.S. leadership in next-generation computing while preparing a workforce equipped to tackle the grand challenges of tomorrow. As modern HPC applications become increasingly data-driven - integrating traditional simulations with machine learning and data analytics - the overhead of moving data between storage and compute units has emerged as a major performance and energy bottleneck. CSDs promise to mitigate this issue by embedding compute engines within storage devices (e.g., solid state devices), allowing select computations to be executed near the data. However, current CSD programming models are low-level, hardware-specific, and lack standardized abstractions, making them difficult to adopt at scale. This project addresses these limitations through five integrated research thrusts: (1) characterizing diverse HPC workloads across real and simulated CSD configurations to identify offload opportunities and performance tradeoffs; (2) exposing CSDs to the software stack via rich abstractions and interfaces that communicate device heterogeneity, memory capacity, and compute capabilities; (3) developing compiler-directed optimizations for code and data placement, loop parallelization, and CSD-to-CSD data migration; (4) designing a runtime system that dynamically manages code fragments offloaded to CSDs, handles multi-application scheduling, and coordinates compute/data mapping with the compiler; and (5) building a simulation platform for futuristic CSD architectures and releasing a benchmark suite tailored to CSD-aware optimizations. Together, these efforts will lower the programming barrier to CSD adoption, enable intelligent orchestration across heterogeneous storage-side compute resources, and advance the state of the art in near-storage computing. Scientifically, this project aims to establish foundational tools, abstractions, and methodologies that accelerate the integration of CSDs into production HPC systems, drive innovation in compiler-runtime co-design for heterogeneous storage environments and enable new levels of energy-efficient performance in data-intensive scientific workloads. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.