CAREER: Process Technology-based Electronic Design Automation Framework Development for Efficient Monolithic Three-dimensional (3D) Integration

About This Grant

A monolithic three-dimensional integrated circuit (M3D IC) is a promising alternative for realizing compact and efficient ICs since conventional two-dimensional integration is limited by lithography and power constraints. In M3D IC technology, the substrate layers are realized sequentially, and these layers are connected through metal inter-layer vias (MIVs). This project addresses significant challenges associated with the process technology for implementing M3D ICs to ensure reliable, compact and efficient designs. The project will facilitate further advances in M3D IC electronic design automation (EDA) methodology to efficiently address the potential challenges in M3D IC technology for full-scale chip designs. The proposed approaches to address the process-dependent challenges in M3D IC will provide future opportunities for M3D IC technology at all design levels – device, circuit, and EDA. The educational goals of this project are to (1) develop activities aiming from high-school students to graduate students that focus on hands-on learning such as a custom lego-like toolkit that captures the EDA optimization problems of M3D ICs and, (2) IC tape-out activities along with emphasizing the need for energy-efficient and compact ICs. This project aims to develop a process-aware reliable and efficient EDA framework for M3D IC designs by addressing the following key concerns: (a) How significant is the impact of MIV on the performance of devices around it in bulk-substrate M3D IC process and how to reduce this impact for efficient and reliable M3D IC designs in this process technology? (b) How beneficial is the back-end-of-line transistor in the ultra-thin selective-substrate process and how to efficiently use this extra dimension for compact and efficient M3D IC designs in this process technology? and (c) How to obtain efficient M3D IC designs for heterogeneous integration considering both bulk-substrate and ultra-thin selective-substrate processes? The first concern will be addressed by developing a custom shielding mechanism based on the M3D IC process to nullify the MIV impact. The second concern will be addressed by developing the design rule-based custom physical design methodology specific to ultra-thin selective substrate process. The third concern will be addressed by combining the above two approaches based on the substrate layer process. The new challenges and exciting optimization problems posed by these approaches will also provide new directions to the EDA research. This project is jointly funded by the Software and Hardware Foundations (SHF) program of the Computing and Communications Foundations (CCF) Division, and the Established Program to Stimulate Competitive Research (EPSCoR) at NSF. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.