ACED: Digital Twin for an Intelligent Electromagnetic Sensor on a Chip (iEM-SoC)

About This Grant

Emerging memory technologies, which facilitate both analog and digital in-memory computations, have captured the attention of commercial and defense sectors as promising replacements for traditional von Neumann computing architectures commonly used in edge sensors. Over the past five years, numerous publications have illustrated the pivotal role of these advanced memory arrays in supporting intelligent systems capable of real-time learning and swift adaptation to changing conditions. Nonetheless, the adoption of these technologies is hampered by the limited availability of mainstream fabrication processes. Currently, TSMC is the predominant provider, which imposes significant cost barriers for research groups eager to develop and test new circuit designs. This innovative digital twin (DT) is designed to validate new designs and propel research and development in this emerging field. It promises to revolutionize design processes across various technical specifications, including frequency bands, signal-to-noise ratios, and spectrum classifiers. The DT has a scalable architecture that facilitates the integration of extensive library models for memory devices and supports these devices across a broad spectrum of material systems and operational scenarios. The potential benefits of this DT, with sensor technology and computational model for advanced receivers, extends to enhancing national security by providing significant advancements in secure communications and threat detection by improving surveillance, data processing, and decision-making capabilities. This project also seeks to improve STEM education and foster a skilled workforce by deepening students' understanding of integrated sensor systems and digital twin technology. The project incorporates a broad educational effort that creates opportunities for students to engage in cutting-edge research. The technologies developed through these student projects are poised to be highly effective across diverse environments and designed to operate on minimal energy budgets, making them economically and environmentally sustainable. This "Emerging Ideas" research effort strategically focuses on leveraging advancements in digital twin technology to fundamentally transform Intelligent Electromagnetic Sensors’ design, development, and testing processes on a Chip (iEM-SoC). This initiative significantly streamlines and enhances the sensor development process by substituting physical sensor models with digital replicas. Chip-based sensors, rapidly advancing across sectors such as autonomous aerial vehicles, industrial robotics, and consumer electronics, demand high sensor resolution, real-time response capabilities, low power consumption, and extended operational times, typically ranging from 0.5 GHz to 1-2 THz. This interdisciplinary endeavor is set to explore the feasibility of developing a Digital Twin for iEM-SoC and aims to achieve multiple objectives: it will produce a digital twin for the design and performance testing of an Intelligent RF Receiver (EM Sensor) capable of real-time operations with extremely low energy consumption; create the first digital model of an analog memory array that accounts for high-frequency effects; provide the first demonstration of a memory array operating system that enables precise segmentation for storing, accessing, and processing analog data with high accuracy (11 bits); and ultimately showcase how a digital twin can facilitate the development of a new class of EM Edge Sensors that surpass the capabilities of current design methodologies. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.