CAREER: Unary Computing in Memory for Fast, Robust and Energy-Efficient Processing

About This Grant

Transferring data between memory and processing units in conventional computing systems is expensive in terms of energy and latency. This data movement consumes significant energy and slows down the processing speed, particularly for data-driven applications such as machine learning workloads. In-memory computing (IMC) is a promising solution to address this issue by performing computations inside memory. However, IMC techniques using emerging memory technologies suffer from multiple key technical challenges that limit their applicability in today’s computing systems. Significant error in the computations is likely with these IMC techniques. The processing latency also increases significantly with data-width; e.g., this is approximately an exponential increase for the multiplication operation. This project addresses the critical challenges with today’s IMC techniques by exploiting a simple and uniform representation of data. Complex arithmetic operations on weighted binary data are transformed into simple bit-wise memory-friendly operations on uniform bit-streams. Successful completion of the project will accelerate and reduce the power and energy consumption of a wide range of applications from biomedicine (e.g., retinal implants), to security (e.g., miniaturized unmanned aerial vehicles), to smart sensors and machine learning (e.g., speech recognition). The team will share the project outcomes, including articles, simulators, and hardware and software toolkits, with the research community. The findings and technical outputs will be integrated into instructional materials for graduate, undergraduate, and K-12 classroom settings. The project activities will engage active participation of graduate and undergraduate students. This project combines the complementary properties of two emerging technologies, IMC and unary computing (UC), to implement a high-performance, reliable, and energy-efficient data processing platform with high computational ability. The presented platform addresses the technical challenges of the IMC techniques using emerging memory technologies. It also addresses the latency and cost-efficiency of the existing UC designs with combinational CMOS logic. The technology explored in this project aims to improve the robustness of IMC operations to noise and variation by processing uniform bit-streams. The platform is highly parallel and effectively scales with the size of computations. It enables fast, accurate, and simple execution of a wide range of arithmetic operations entirely in memory. It enjoys independent bit-wise operations, avoiding long chains of operations, an important source of in-efficiency in today’s IMC techniques. The target platform is general and can be used for various applications. This project is jointly funded by the Software and Hardware Foundations (SHF) program in the Computing and Communication Foundations (CCF) division, and the Established Program to Stimulate Competitive Research (EPSCoR). This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.