Collaborative Research: Memtransistor with Enhanced Functionality Enables Energy-efficient AI Hardware

About This Grant

Modern artificial intelligence (AI) is inspired by the brain’s cognitive functions but relies on models that differ greatly from biological systems and consume substantial energy during training and inference. According to the Semiconductor Research Corporation, continued scaling of logic devices and increasing model complexity could push machine learning energy consumption beyond global energy production capacity—an unsustainable trajectory. In contrast, the human brain performs complex computations with vastly lower energy. To bridge this gap, this project proposes a novel three-terminal transistor that integrates interconnected long-term and short-term memory—an essential yet underutilized feature of the brain—within a single device to improve energy efficiency, simplify architectures, and enable new capabilities. The device will advance two computing paradigms: Spiking Neural Networks and Physical Reservoir Computing, supporting scalable, high-performance, energy-efficient hardware for temporal signal processing, neuromorphic computing, AI, and post-silicon technologies. It will also drive progress in fabrication methods, learning algorithms, and system architectures that leverage the unique properties of the proposed materials and devices. The interdisciplinary nature of this project—spanning engineering, physics, chemistry, neuroscience, nonlinear dynamics, and AI—will provide students with exceptional scientific training and prepare them to contribute across multiple fields. This project aims to develop the Diffusive Ferroelectric Field-Effect Transistor (DFeFET), a novel brain-inspired highly scalable memory device that integrates long-term (non-volatile) and short-term (volatile) memory in an interconnected manner. The DFeFET combines engineered drain contact metals and amorphous oxide semiconductor (AOS) channels in ferroelectric-gated field-effect-transistors (FeFETs) to achieve controllable volatile hysteresis in drain current–voltage characteristics. Volatile memory arises from reversible ion or vacancy exchange at the drain/channel interface, modulated by gate voltage and gradual gate polarization switching, enabling co-located, co-dependent memory akin to the human brain. This device is expected to deliver enhanced energy efficiency and functionality for brain-inspired computing. In particular, it will advance two neuromorphic architectures: (i) Spiking Neural Networks (SNNs) with Spike Frequency Adaptation (SFA) and (ii) CMOS-compatible Physical Reservoir Computing (PRC). SFA, which self-regulates neuron spiking through internal negative feedback, improves SNN performance and energy efficiency but typically requires complex circuitry. DFeFET will be used to enable three bio-inspired SFA mechanisms with improved energy efficiency and reduced area. Additionally, the research aims to develop a novel PRC architecture with task-specific timescale adaptability and coupled higher-order nonlinear dynamics. It will leverage CMOS-compatible DFeFETs to build both reservoir and readout layers using a single device for efficient chip integration. For both neuromorphic architectures, a corresponding device-algorithm co-optimization framework will also be developed to optimize the accuracy, latency, area and energy efficiency of the proposed analog implementations. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.