Closed-Loop kT/C Noise Cancellation for Sampling Circuits with Unprecedented Sensitivity

About This Grant

Thermal noise presents the most fundamental limit to the achievable signal-to-noise ratio (SNR) in analog electronic circuits. To suppress thermal noise, many scientific instruments used in fields such as radio astronomy, high-energy particle colliders, and emerging superconducting quantum computers require cryogenic cooling, which significantly increases their cost and consumes more energy. For most commercial and industrial applications where cryogenic cooling is too expensive to employ, the only solution for reducing sampled thermal noise in discrete-time electronic circuits is to use a larger sampling capacitor, which significantly increases the size and cost of electronic components and is impractical for integrated semiconductor chips. This underscores the need to search for a new game-changing circuit design solution, which is the focus of the proposed thermal noise cancellation research in this project. The intriguing challenges and intellectual allure surrounding the noise-cancellation analog electronic circuit design have the potential to motivate undergraduate and graduate students toward this electrical engineering discipline, igniting interest not only in analog electronics but also in the broader spectra of science and engineering. Building upon this initiative, the outreach plan involving both the University of Texas at Dallas and the University of Texas Rio Grande Valley holds the potential to impact both institutions and the broader communities in the North and South Texas regions, thereby fostering a strong educational component that will contribute to the future workforce development in the semiconductor industry. In this project, the principal investigator (PI) introduces a closed-loop noise-cancellation technique to suppress thermal noise in signal-sampling circuits (a.k.a. kT/C noise, where k is the Boltzmann’s constant, T is the absolute temperature, and C is the sampling capacitance) while improving the linearity of the sample-and-hold (S/H) circuit over a prior open-loop noise-cancellation technique. The insight of the closed-loop technique is based on and derived from an accurate analysis of the existing open-loop counterpart’s limitations, primarily its signal-feedthrough nonlinearity problem associated with the delayed secondary sampling operation. The necessity of employing a large ac-coupling capacitor for noise storage and a two-stage operational amplifier presents several design challenges, including higher power, larger area, and compromised analog performance. The project will develop a new closed-loop architecture to eliminate signal-feedthrough distortion without a large noise-storage capacitor and a two-stage amplifier. Additionally, the research team will incorporate a digital predictive amplifier-swing neutralization technique to further enhance the noise-cancellation performance of and improve signal linearity in the closed-loop architecture. The project will demonstrate the new closed-loop architecture using a semiconductor chip prototype implemented in a 16-nm silicon CMOS technology, with a targeted size reduction of front-end sampling capacitance by 20 times as compared to a state-of-the-art commercial product. To facilitate benchmarking the high dynamic range of the S/H circuit achieved by the new noise cancellation technique, a 16-bit pipelined successive-approximation-register (SAR) analog-to-digital converter (ADC) will be integrated on the same prototype chip. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.