SBIR Phase I: Microscale Selective Sintering for High Throughput Metal Additive Manufacturing of Interconnects in Semiconductor Packaging

About This Grant

The broader/commercial impact of this SBIR Phase I project is the commercialization of microscale selective laser sintering (μ-SLS), a new 3D printing technology that drastically lowers the cost and time required to produce custom interconnect structures for semiconductor chips. Currently, the high cost of creating specialized chip interconnects limits innovation in critical fields such as national defense, medical devices, and scientific research. This project introduces an advanced 3D printing process that builds microscopic metal connections on chips directly from a digital file, eliminating the need for expensive custom tooling. This innovation significantly reduces the financial barrier for producing small batches of high-performance chips, enabling faster prototyping and development. The initial market will be defense electronics, followed by expansion into other specialized sectors. The business model involves licensing this proprietary technology to equipment manufacturers, ensuring widespread adoption and a durable competitive advantage based on a unique combination of speed, precision, and flexibility. By strengthening domestic manufacturing capabilities and enabling new technologies, this project serves the national interest by advancing national security, economic prosperity, and scientific progress. This Small Business Innovation Research (SBIR) Phase I project addresses the technical challenges of creating a viable additive manufacturing process for semiconductor packaging. It provides a cost-effective alternative to traditional lithography for the low-volume, high-mix production required by custom semiconductor applications. This project investigates microscale selective laser sintering (μ-SLS), a novel process which uses a digital micromirror device to pattern laser energy and fuse metal nanoparticles into 3D interconnect structures. The main research objective is to transition this process from glass substrates to industry-standard silicon wafers. Key research activities include updating thermal and coating models, fabricating multi-layer copper test structures, and characterizing their properties. Anticipated results include a validated process for producing copper interconnects on silicon with sufficient mechanical adhesion (>5 MPa) and electrical conductivity (>50% of bulk copper). This work will also establish the limits of key material properties, such as the Coefficient of Thermal Expansion, Young's Modulus, and shear strength, which are critical for thermomechanical reliability of the fabricated electronic package. These results will define the operational limits for future device design and demonstrate the technology's commercial potential. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.