DESC: Type I: Water- and Carbon-Aware Design of Chiplet-based Systems with Reconfigurability for AI in Datacenters

About This Grant

As artificial intelligence (AI) applications become increasingly central to our daily lives, the datacenters that serve these applications are growing rapidly. However, this growth comes with a significant environmental cost. These datacenters rely on computer chips whose design, manufacturing, and operation consume substantial amounts of energy, water, and resources, posing challenges to environmental sustainability. This project addresses this critical challenge by rethinking how we design computer chips that power AI in today’s datacenters. Current chip design methodologies often overlook their full environmental footprint, particularly the water and energy impacts across the chip lifecycle. As AI workloads expand, these factors, especially in chip manufacturing and datacenter cooling, are becoming increasingly important to sustainable computing. This project directly addresses these challenges by introducing three key strategies for a sustainability-aware approach to chip design. First, this project develops new models, tools, and metrics to quantify the environmental footprint of chips throughout their lifecycle - from design and manufacturing to deployment and eventual end-of-life. It includes detailed modeling of water and energy consumption, particularly for chip fabrication and chip cooling. Second, the project introduces a framework for splitting large complex chips into small modular chiplets, and replacing them with reconfigurable chiplets allowing their reuse across multiple different AI applications. This increases their operation lifetime in datacenters reducing wastage and cost. Third, the project builds software to optimize chip floor planning and interconnect design to minimize cooling requirements, fabrication energy and environmental costs. This project supports NSF’s mission to advance American innovation, economic prosperity, and global leadership in emerging technologies. It strengthens U.S. leadership in AI and datacenter infrastructure by developing advanced tools to design more efficient, cost-effective computer chips that power these systems. By reducing unnecessary energy and water use, the project improves operational efficiency and lowers costs which are key priorities for sustainable growth and resilient infrastructure. Additionally, it supports workforce development by engaging K–12 and community college students in applied learning experiences that prepare them for high-demand jobs in AI, semiconductors, and advanced manufacturing. This project aims to develop a framework for designing computing chips for AI datacenters. The overarching goal is to minimize the environmental footprint (EFP), including both carbon footprint (CFP) and water footprint (WFP), across the lifecycle of computing - from design to manufacturing to use. The project is structured around three thrusts: (1) Developing models and metrics for evaluating EFP with a special emphasis of WFP, (2) Disaggregating Systems-on-Chip (SoCs) into chiplet-based SiPs with a focus on integrating Field Programmable Gate Array (FPGA) chiplets, and (3) Physical design of chiplet-based Systems-in-Package (SiPs) considering EFP as a metric of optimization. To support EFP-aware chip design, the project introduces new metrics, such as Performance-per-Unit-EFP, to guide architectural and physical optimizations. The modeling framework will extend beyond traditional CFP-based models by incorporating water usage in both semiconductor fabrication and datacenter cooling. A design-space exploration (DSE) framework will be developed using graph-based partitioning methods to decompose SoCs into SiPs. This DSE process will optimize across multiple objectives, including bandwidth, latency, and power, while minimizing overall EFP. Furthermore, the project will model the EFP impact of physical implementation choices, including placement, routing, and 3D stacking, and integrate these models into traditional place-and-route algorithms to enable EFP-aware physical design. This project pioneers the integration of EFP with tools and methodologies used for the architecture and design of future chips. By incorporating WFP, it expands the scope of current sustainable computing research. The open-source software for SoC disaggregation and EFP-aware physical design will help accelerate the adoption of sustainable design practices in the chip design industry. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.