SHF: Small: A Communication-Centric Validation Framework for System-on-Chip Designs

About This Grant

The rapid growth of smart, connected computing devices in critical fields like transportation, industrial automation, healthcare, and finance has made our society increasingly dependent on their safe, secure, and reliable operation. System-on-Chip (SoC) designs are the hardware backbone of these systems. An SoC design integrates a large number of pre-designed components that coordinate through sophisticated system-level protocols to realize various system functions. The components may contain vulnerabilities due to malicious modification or design mistakes, which can be exploited to leak secrets or cause system malfunction. Therefore, SoC designs must undergo comprehensive and rigorous validation to ensure safety and security before deployment in critical applications. Although large bodies of verification and validation methods have been developed, the existing methods are too slow to thoroughly verify large complex SoC designs before their silicon fabrication (the "pre-silicon" stage) while the existing solutions are not useful for validating fabricated chips (the "post-silicon" stage) since not all internal signals can be observed or analyzed. These challenges prevent achieving the high level of confidence needed for SoCs in critical applications. This project aims to develop a holistic framework that integrates novel solutions to overcome the limitations of the existing pre-silicon verification and post-silicon validation methods, enabling efficient and comprehensive SoC validation across the entire design flow. The resulting impacts of this research include substantially improved productivity and quality of SoC validation, ultimately providing greater assurance in deployed SoC designs, technology transfer through close collaboration with industry on real-world designs with practical significance, and workforce development through recruitment and training of students from diverse backgrounds. Prior studies have shown that intricate communications among the components in a SoC design are a major source of errors. This project focuses on representing and analyzing cross-block communications to reduce validation complexity. Models characterizing such communications serve as a unifying thread to tie validation activities across both pre-silicon and post-silicon stages. The project consists of three tasks. Task 1 develops solutions to facilitate efficient and comprehensive pre-silicon full system validation based on a communication-centric methodology. Task 2 develops approaches to learning system communication models from the SoC execution traces generated during the full system validation to facilitate analysis and debug. Task 3 develops new machine learning methods utilizing the communication models from Task 2 to enhance the observability of the post-silicon traces for more efficient post-silicon debug. Throughout this project, the power of recent deep sequence modeling approaches, such as the transformer model and its variants, as well as sequential pattern mining methods are exploited in novel ways to achieve the technical aims of this project. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.