Collaborative Research: CSR: Small: SOCRATES: Post-Silicon Validation of Hardware-Software Interactions

About This Grant

Modern microelectronic computer chips include considerable low-level software critical to the system functionality. This software must be ready when the system is shipped to customers, and it is difficult to modify post deployment. One approach to ensure that the low-level software works as intended on the hardware is to produce a pre-production version of the chip for software/hardware testing, in a method referred to as "post-silicon validation". Post-silicon software validation is a highly complex and expensive activity requiring significant upfront planning and accounting for significant validation cost. Unfortunately, there has been little research in post-silicon software validation; existing research focuses primarily on functional and security validation of the underlying hardware. The project addresses this crucial problem via a comprehensive foundational paradigm and tool suite to streamline post-silicon software validation. The project’s key novelties include a unique architecture for observing hardware-software interaction in a silicon platform, methods to generate appropriate test inputs for exercising these interactions, and an objective metric to identify the quality of validation. The project’s broader impacts and significance include a pathway to derive high assurance in correctness of modern microelectronics systems that include tightly interacting hardware and software components, as well as creation of hands-on training modules to enable awareness in the problem for undergraduate and high-school students. The technical insight of the project is that a comprehensive post-silicon validation methodology requires cooperation of three components: an architecture for recording and transporting system events providing observability of the system internals during execution, a test generation methodology that is observability-aware, and a new coverage metric that accounts for the test scenarios being exercised and events being observed. The project realizes this insight through cooperative application of a novel architecture for collecting and synchronizing hardware-software events and a design automation flow that integrates this architecture with test generation and coverage calculation. The methodology targets validation of open-source System-on-Chip designs as well as emergent commercial systems. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.