National Chip Design Hub: University of Chicago Advanced Chip Design Enablement – 3D (ACE-3D)

About This Grant

The development of three-dimensional heterogeneously integrated circuits (3D HI) marks a significant advancement in semiconductor technology, offering greater efficiency, performance, and compactness for applications ranging from consumer electronics to national defense. By enabling the vertical stacking of diverse chip components into tightly integrated systems, 3D HI unlocks new possibilities for systems built with diverse and advanced functionalities in cost efficient packages. However, despite its transformative potential, the widespread adoption of 3D HI remains limited due to challenges in research capacity and implementation, which requires significant financial investment that is typically confined to large-scale foundries. This makes it inaccessible to many academic institutions and companies. The current landscape of 3D HI mirrors that of two-dimensional (2D) Very Large Scale Integration (VLSI) in its early days, when a lack of access, standards, and trained designers posed major barriers. To unlock the full potential of 3D HI and accelerate its integration into mainstream semiconductor design, there is a pressing need to democratize access, establish standard design practices, broaden utilization across sectors, and train a skilled workforce. This project establishes the ACE-3D Chip Design Hub as a national resource to address these gaps and advance U.S. innovation and economic competitiveness in 3D HI chip design. The ACE-3D Hub will focus on advanced design challenges unique to 3D integration, such as multi-layer architectures, thermal management, and bonding technologies. The Hub will develop and support an ecosystem that enables 3D-HI chip design and advanced packaging by: (1) providing training and education for students from high school to advanced degree levels; (2) creating a user-friendly Integrated Circuit (IC) Design Ecosystem for 3D HI with pathways enabled for advanced fabrication and packaging multi-project wafers (MPWs), and (3) providing access to expert support, community involvement, and infrastructure to members with open-source methodologies, test infrastructure, and multi-level training opportunities through workshops and intensive courses in collaboration with national labs. A core impact of this Hub will be through an expert-guided ecosystem that supports users at every stage of the design process. The Hub will provide coordinated access to experienced chip designers, open-source reference methodologies, and a curated library of instructional materials (labs, tutorials, and design exercises) that are tailored to 3D HI concepts and shared through the NSF Chip Design Hub program, advancing next-generation semiconductor design and creating a pipeline of U.S. talent equipped to address future challenges in computing, communications, and sensing innovation. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.